1. Field of the Invention
The present invention relates to semiconductor fabrication, and in particular, to ting spacers that are formed along the sidewalls of a semiconductor gate structure.
2. Description of the Related Art
Traditional semiconductor spacers are formed along the sidewalls of a transistor device using various materials, such as oxide, polysilicon and nitrides.
Methods for lateral trimming of spacers are provided in accordance with the present invention. A method in accordance with the invention may regulate and repeatably trim a nitride or polysilicon spacer. In one embodiment, the method controllably trims a multi-film stack spacer utilizing a xe2x80x9cself-limitingxe2x80x9d etch technique. Modulating the width of a spacer during a process flow can improve device performance by allowing additional source and drain to be implanted during the process and increased source and drain area dimensions.
In one embodiment, the method uses a plasma dry etch process that advantageously controls the ratio of lateral-to-vertical etch rates in spacer etch trimming. The etching technique is predominantly chemical in nature and enhances lateral trim capabilities.
One aspect of the invention relates to a method of forming spacers proximate to a gate structure. The method comprises forming a first layer over a gate structure and a substrate; etching the first layer to form a first set of spacers proximate to the gate structure; forming a second layer over the substrate, the first set of spacers and the gate structure; forming a third layer over the second layer; etching the third layer to form a second set of spacers proximate to the first set of spacers; and dry etching the second set of spacers with a plasma, wherein the second layer prevents the etching of the second set of spacers from substantially affecting the first set of spacers.
Another aspect of the invention relates to a transistor structure formed by the method described above.
Another aspect of the invention relates to a system configured to form a first AU layer over a gate structure and a substrate; etch the first layer to form a first set of spacers proximate to the gate structure; form a second layer over the substrate, the first set of spacers and the gate structure; form a third layer over the second layer; etch the third layer to form a second set of spacers proximate to the first set of spacers; and etch the second set of spacers, wherein the second layer prevents the etching of the ill second set of spacers from substantially affecting the first set of spacers.